(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to create a bit line structure, for a semiconductor device.
(2) Description of Prior Art
Bit line structures, for semiconductor devices such as dynamic random access memory, (DRAM), have been fabricated using conductive layers such as doped polysilicon, metal silicide, or metal. In addition these same bit line structures have been capped, or encapsulated with silicon nitride, to allow self-alignment of the bit line structure to underlying structures, or to allow self-alignment of subsequent overlying structures to the bit line structure, to be accomplished. The use of a high dielectric constant, silicon nitride layer, as a capping layer for the bit line structures, can howver result in performance degrading coupling capacitances, as a result of the proximity of adjacent conductive structures, to the silicon nitride capped, bit line structure. A solution used to lower the performance degrading coupling capacitance, has been the use of a silicon oxide layer, located between the overlying silicon nitride layer, and the underlying, conductive bit line shape. The use of the lower dielectric constant silicon oxide layer, results in a reduction in coupling capacitance when compared to counterparts fabricated only the silicon nitride capping layer.
To further increase device performance the bit line structure can be formed from tungsten, offering a sheet resistance between about 1 to 3 ohms/square, compared to counterparts fabricated from tungsten silicide layers, with a sheet resistance between about 5 to 10 ohms/square. However during the formation of the silicon oxide layer, used to reduce coupling capacitance, the surface of the underlying tungsten shape can be oxidized, resulting in unwanted consumption of tungsten, increasing the resistance of the bit line structure. This invention will teach a process sequence in which a silicon oxide layer can be used as part of a composite, or sandwich, capping layer, however avoiding the risk of oxidizing the underlying tungsten bit line. This is accomplished by initially depositing a thin underlying silicon nitride, directly on the tungsten layer, used for the bit line, followed by the deposition of the needed silicon oxide layer, and of the overlying silicon nitride layer, used for self-alignment purposes. After patterning a silicon nitride capped, tungsten bit line structure is realized, featuring the use of the silicon oxide layer, used to reduce coupling capacitance, but placed on a thin underlying silicon nitride layer, to avoid reaction with tungsten. Prior art, such as Sung et al, in U.S. Pat. No. 5,879,986, describe a silicon nitride encapsulated bit line structure, however that prior art does not feature the use of a silicon oxide layer, as a component of the capping layer, and thus allowing performance degrading coupling capacitances to occur.